The present invention relates generally to computer memory, and more specifically to probabilistic multi-tier error correction in not-and (NAND) flash memory.
Phase change memories (PCMs) and flash memories are examples of non-volatile memories with limited endurance (also referred to as a “limited life”). Such memories have limited endurance in the sense that after undergoing a number of writing cycles (RESET cycles for PCM, and program/erase cycles for flash memory), the memory cells wear out and can no longer reliably store information
NAND flash memories are increasingly being used as non-volatile storage media in both consumer and enterprise applications. One characteristic of contemporary NAND flash memory devices is that they display strong data dependent and device dependent error modes, often with inter-cell dependencies. The programming and charge levels of surrounding cells may have a direct impact on the error conditions that occur in adjoining cells.
NAND memory may also be prone to random errors caused during the programming stage and due to retention errors. Typical error effects include background pattern dependency (BPD) errors, bit-line disturbance (BLD) errors, page and program disturbance (PGM) errors, and floating gate coupling (FGC) errors. The effect of these types of errors can be mitigated in some cases by imposing restrictions on the memory use. By stipulating, for example, that a block of memory can only be written to sequentially, some of these errors may be eliminated or reduced. Such restrictions however, may have unwanted side effects, such as increasing write latency, increasing wear, and write amplification. In addition, different program levels may have non-identical error transition probabilities.